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june 2001 C revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection tisp4125h3bj/tisp4219h3bj, tisp4125m3bj/tisp4219m3bj lcas ring and tip protection pairs bidirectional thyristor overvoltage protectors description customized voltage for lcas protection battery-backed ringing ............................................. 87 v rms ground-backed ringing ........................................... 101 v rms low differential capacitance .................................39 pf max. .................................................... ul recognized components rated for international surge wave shapes these protector pairs have been formulated to limit the peak voltages on the line terminals of the ?581/2/3 lcas (line card ac cess switches) type devices. an lcas may also be referred to as a solid state relay, ssr, i.e. a replacement of the conventional electro-mecha nical relay. overvoltages are normally caused by a.c. power system or lightning flash disturbances which are induced or conducted on to the telephone line. these overvoltages are initially clipped by protector breakdown clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. this low-voltage on state causes the current resulting from the overvoltage to b e safely diverted through the device. for negative surges, the high crowbar holding current prevents d.c. latchup with the slic current, as the s urge current subsides. each protector consists of a symmetrical voltage-triggered bidirectional thyristor. they are guaranteed to voltage limit and wi thstand the listed international lightning surges in both polarities. how to order device symbol smbj package (top view) device v drm v v (bo) v lcas terminal ?125 100 125 tip ?219 180 219 ring wave shape standard i tsp a h3 series m3 series 2/10 s gr-1089-core 500 300 8/20 s iec 61000-4-5 300 220 10/160 s fcc part 68 250 120 10/700 s itu-t k.20/21/45 200 100 10/560 s fcc part 68 160 75 10/1000 s gr-1089-core 100 50 12 t(a) r(b) mdxxbge t r sd4xaa terminals t and r correspond to the alternative line designators of a and b *rohs directive 2002/95/ec jan 27 2003 including annex device package carrier tisp4125h3bj bj (j-bend do-214aa/smb) embossed tape reeled tisp4125h3bjr tisp4219h3b j tisp4219h3bjr tisp4125m3bj tisp4125m3bjr tisp4219m3bj tisp4219m3bjr tisp4125h3bjr-s tisp4219h3bjr-s tisp4125m3bjr-s tisp4219m3bjr-s for standard termination finish order as for lead free termination finish order as *r o h s c o m p l i a n t v e r s i o n s a v a i l a b l e
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. absolute maximum ratings, t a = 25 c (unless otherwise noted) tisp4xxxh3/m3bj series for lcas protection recommended operating conditions component condition min typ max unit r s se ries current limiting r esistor gr -1089-core first-level surge survival 0 ? gr -1089-core first-level and second-level surge survival 0 ? k. 20, k.21 and k.45 coordination pass with a 400 v primary protector 6 ? v ri ng ac ringin g vo ltage figure 12, v bat = -48 v 2.5 v, r1= r2 = 300 ? , 0 c < t a < +85 c battery-backed 87 v rms v rms gr ound-backed 101 tisp4125h3bj & tisp4219h3bj rating symbol value unit repetitive peak off-state voltage, (see note 1) ?125 ?219 v drm 100 180 v no n-repetitive peak on-state pulse current (see notes 2 and 3) i tsp a 2/10 s( gr - 1089-core, 2/10 s voltage wave shape) 500 8/20 s (iec 61000-4-5, 1.2/50 s voltage, 8/20 current combination wave generator) 300 10/160 s(f cc part 68, 10/160 s voltage wave shape) 250 5/200 s( vde 0433, 10/700 s vo ltage wave shape) 220 0.2/310 s (i3124, 0.5/700 s voltage wave shape) 200 5/310 s( i tu-t k.20/21, 10/700 s voltage wave shape) 200 5/310 s(ftz r 12, 10/700 s voltage wave shape) 200 10/560 s( f cc part 68, 10/560 s voltage wave shape) 160 10/1000 s( gr - 1089-core, 10/1000 s voltage wave shape) 100 no n-repetitive peak on-state current (see notes 2, 3 and 4) i tsm 55 60 2.1 a 20 ms (50 hz) full sine wave 16.7 ms (60 hz) full sine wave 1000 s 50 hz/60 hz a.c. in itial rate of rise of on-state current, exponential current ramp, maximum ramp value < 200 a di t /dt 400 a/ s j unction temperature t j -40 to +150 c st or age temperature range t stg -65 to +150 c no te s: 1. see applications information for voltage values at lower temperatures. 2. initially, the tisp4xxxh3bj must be in thermal equilibrium with t j =25 c. 3. the surge may be repeated after the tisp4xxxh3bj returns to its initial conditions. 4. eia/jesd51-2 environment and eia/jesd51-3 pcb with standard footprint dimensions connected with 5 a rated printed wiring tr ac k widths. see figure 10 for the current ratings at other durations. derate current values at -0.61 %/ c for ambient tem peratures above 25 c.
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection electrical characteristics, tisp4xxxh3, t a = 25 c (unless otherwise noted) thermal characteristics parameter t est conditions min typ max unit i drm repeti tive peak off- st ate current v d = v drm t a = 25 c t a = 85 c 5 10 a v (bo) br eakover voltage dv/dt = 250 v/ms, r sour ce = 300 ? ?125 ?219 125 219 v v (bo) impulse br eakover voltage dv/dt 1000 v/ s, linear voltage ramp, maximum ramp value = 500 v di/dt = 20 a/ s, linear current ramp, maximum ramp value = 10 a ?125 ?219 134 229 v i (bo) br eakover current dv/dt = 250 v/ms, r sour ce = 300 ? 0.15 0.6 a v t on-state voltage i t = 5a, t w = 100 s 3v i h hold ing current i t = 5a, di/dt=+/-30ma/ms 0.15 0.6 a dv/dt crit ical rate of rise of o ff- st ate voltage linear voltage ramp, maximum ramp value < 0.85v drm 5 kv/ s i d of f-state current v d = 50 v t a = 85 c 10 a c off off-state capacitance f=1mhz, v d =1v rms, v d =0, f=1mhz, v d =1v rms, v d =-1v f=1mhz, v d =1v rms, v d =-2v f=1mhz, v d =1v rms, v d =-50v f=1mhz, v d =1v rms, v d = -100 v (s ee note 5) 80 71 65 30 23 90 79 74 35 28 pf note 5: to avoid possible voltage clipping, the 4125 is tested with v d =-98v. parame ter test conditions min typ max unit r ja junction to free air thermal resistance eia/jesd51-3 pcb, i t = i tsm(1000) , t a = 25 c, (see note 6) 113 c/w 265 mm x 210 mm populated line card, 4-layer pcb, i t = i tsm(1000) , t a = 25 c 50 no te 6: eia/jesd51-2 environment and the pcb has standard footprint dimensions connected with 5 a rated printed wiring track width s.
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection absolute maximum ratings, t a = 25 c (unless otherwise noted) rating symbol value unit repetitive peak off-state voltage, (see note 7) ?125 ?219 v drm 100 180 v no n-repetitive peak on-state pulse current (see notes 8 and 9) i tsp a 2/10 s( gr - 1089-core, 2/10 s voltage wave shape) 300 8/20 s (iec 61000-4-5, 1.2/50 s voltage, 8/20 current combination wave generator) 220 10/160 s(f cc part 68, 10/160 s voltage wave shape) 120 5/200 s( vde 0433, 10/700 s vo ltage wave shape) 110 0.2/310 s (i3124, 0.5/700 s voltage wave shape) 100 5/310 s( i tu-t k.20/21, 10/700 s voltage wave shape) 100 5/310 s(ftz r 12, 10/700 s voltage wave shape) 100 10/560 s( f cc part 68, 10/560 s voltage wave shape) 75 10/1000 s( gr - 1089-core, 10/1000 s voltage wave shape) 50 no n-repetitive peak on-state current (see notes 8, 9 and 10) i tsm 30 32 2.1 a 20 ms (50 hz) full sine wave 16.7 ms (60 hz) full sine wave 1000 s 50 hz/60 hz a.c. in itial rate of rise of on-state current, exponential current ramp, maximum ramp value < 200 a di t /dt 300 a/ s j unction temperature t j -40 to +150 c st or age temperature range t stg -65 to +150 c no te s: 7. see applications information for voltage values at lower temperatures. 8. initially, the tisp4xxxm3bj must be in thermal equilibrium with t j =25 c. 9. the surge may be repeated after the tisp4xxxm3bj returns to its initial conditions. 10.eia/jesd51-2 environment and eia/jesd51-3 pcb with standard footprint dimensions connected with 5 a rated printed wiring track widths. see figure 11 for the current ratings at other durations. derate current values at -0.61 %/ c for ambient tem peratures above 25 c. recommended operating conditions component condition min typ max unit r s se ries current limiting r esistor gr -1089-core first-level surge survival 10 ? gr -1089-core first-level and second-level surge survival 12 ? k. 20, k.21 and k.45 coordination pass with a 400 v primary protector 6 ? v ri ng ac ringin g vo ltage figure 12, v bat = -48 v 2.5 v, r1= r2 = 300 ? , 0 c < t a < +85 c battery-backed 87 v rms v rms gr ound-backed 101 tisp4125m3bj & tisp4219m3bj
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection electrical characteristics, tisp4xxxm3, t a = 25 c (unless otherwise noted) parameter t est conditions min typ max unit i drm repeti tive peak off- st ate current v d = v drm t a = 25 c t a = 85 c 5 10 a v (bo) br eakover voltage dv/dt = 250 v/ms, r sour ce = 300 ? ?125 ?219 125 219 v v (bo) impulse br eakover voltage dv/dt 1000 v/ s, linear voltage ramp, maximum ramp value = 500 v di/dt = 20 a/ s, linear current ramp, maximum ramp value = 10 a ?125 ?219 132 226 v i (bo) br eakover current dv/dt = 250 v/ms, r sour ce = 300 ? 0.15 0.6 a v t on-state voltage i t = 5a, t w = 100 s 3v i h hold ing current i t = 5a, di/dt=+/-30ma/ms 0.15 0.6 a dv/dt crit ical rate of rise of of f- st ate voltage linear voltage ramp, maximum ramp value < 0.85v drm 5 kv/ s i d of f-state current v d = 50 v t a = 85 c 10 a c off off-state capacitance f=1mhz, v d =1v rms, v d =0, f=1mhz, v d =1v rms, v d =-1v f=1mhz, v d =1v rms, v d =-2v f=1mhz, v d =1v rms, v d =-50v f=1mhz, v d =1v rms, v d = -100 v (s ee note 11) 62 56 52 26 21 74 67 62 31 25 pf note 11: to avoid possible voltage clipping, the 4125 is tested with v d =-98v. thermal characteristics parame ter test conditions min typ max unit r ja junction to free air thermal resistance eia/jesd51-3 pcb, i t = i tsm(1000) , t a = 25 c, (see note 12) 115 c/w 265 mm x 210 mm populated line card, 4-layer pcb, i t = i tsm(1000) , t a = 25 c 52 no te 12: eia/jesd51-2 environment and the pcb has standard footprint dimensions connected with 5 a rated printed wiring track wid t hs.
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection parameter measurement information figure 1. voltage-current characteristic for t and r terminals all measurements are referenced to the r terminal -v v drm i drm v d i h i t v t i tsm i tsp v (bo) i (bo) i d quadrant i i switching characteristic +v +i v (bo) i (bo) v d i d i h i t v t i tsm i tsp -i quadrant iii switching characteristic pmxxaab v drm i drm
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection tisp4xxxh3bj typical characteristics figure 2. off-state current vs junction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 |i d | - off-state current - a 0?01 0?1 0? 1 10 100 tchag v d = 50 v figure 4. on-state current vs on-state voltage v t - on-state voltage - v 0.7 1.5 2 3 4 5 7 110 i t - on-state current - a 1.5 2 3 4 5 7 15 20 30 40 50 70 150 200 1 10 100 t a = 25 c t w = 100 s tc4hacc figure 5. normalized holding current vs junction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 normalized holding current 0.4 0.5 0.6 0.7 0.8 0.9 1.5 2.0 1.0 tc4had figure 3. normalized breakover voltage vs junction temperature t j - junction temperature - c -25 0 25 50 75 100 125 150 normalized breakover voltage 0.95 1.00 1.05 1.10 tc4haf
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection tisp4xxxm3bj typical characteristics off-state current vs junction temperature t j - junction temperature - c off-state current - a figure 6. -25 0 25 50 75 100 125 150 |i d | - 0?01 0?1 0? 1 10 100 tcmag v d = 50 v normalized breakover voltage vs junction temperature figure 7. t j - junct ion temperature - c normalized breakover voltage -25 0 25 50 75 100 125 150 0.95 1.00 1.05 1.10 tc4maf on-state current vs on-state voltage on-state current - a figure 8. v t - on-state voltage - v 0.7 1.5 2 3 4 5 7 110 i t - 1.5 2 3 4 5 7 15 20 30 40 50 70 1 10 100 t a = 25 c t w = 100 s tc4macb normalized holding current vs junction temperature t j - junction temperature - c normalized holding current figure 9. -25 0 25 50 75 100 125 150 0.4 0.5 0.6 0.7 0.8 0.9 1.5 2.0 1.0 tc4mad
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection rating information tisp4xxxh3bj figure 10. non-repetitive peak on-state current vs current duration t - current duration - s 0? 1 10 100 1000 i tsm(t) - non-repetitive peak on-state current - a 1.5 2 3 4 5 6 7 8 9 15 20 30 10 ti4hac v gen = 600 vrms, 50/60 hz r gen = 1.4*v gen /i tsm(t) eia/jesd51-2 environment eia/jesd51-3 pcb t a = 25 c tisp4xxxm3bj figure 11. non-repetitive peak on-state current vs current duration t - current duration - s non-repetitive peak on-state current - a 0? 1 10 100 1000 i tsm(t) - 1.5 2 3 4 5 6 7 8 9 15 20 30 10 ti4mac v gen = 600 vrms, 50/60 hz r gen = 1.4*v gen /i tsm(t) eia/jesd51-2 environment eia/jesd51-3 pcb t a = 25 c
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection applications information introduction these protector pairs have been designed to limit the peak voltages on the line terminals of ?581/7582/7583 lcas (line card ac cess switch) parts. an lcas may also be referred to as a solid-state relay, ssr, i.e. a replacement of the conventional electro-mechanical r elay. the ?581 lcas has two solid-state switches which connect the telephone line to the line card slic (subscriber line interface c ircuit), figure 12, sw1 and sw2. a further two solid-state switches connect the telephone ringing generator to the line, figure 12, sw3 and sw4 . applied 5-volt logic signals control the condition of the switches to perform the functions of line disconnect, connection to the slic and application of ringing. if excessive long-term overdissipation occurs, a thermal sensor activates thermal shutdown and opens the switches. the slic side of switches sw1 and sw2 is limited in voltage by internal protectors th3 and th4. the line-side of the lcas is voltage limited by the two tisp parts. fi gure 12. basic lcas arrangement ring relay slic relay ring generator sw5b sw5a r1 r2 v bat v ring th1 th2 th3 th4 slic v bat tisp4125m3 or tisp4125h3 ring tip sw3 sw4 sw1 sw2 control logi c lcas tisp4219m3 or tisp4219h3 ai4xaq additional functions are provided by the ?582 (line test access) and the ?583 (test-in and test-out access). up to three conv entional electro- mechanical relays may be replaced by the lcas. the resulting size reduction can double the line density of a line card. this document covers the types of overvoltage protection required by the ?581 lcas and how the tisp part voltages are selected to provide these requirements. the lcas ?582 and ?583 are also covered as the additional switches used in these parts are simila r to the ?581.
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection lcas switch ratings equivalent circuit figure 13 shows the lcas switch voltage ratings as breakdown diodes, which must not be allowed to conduct. each switch has thre e diodes; one between poles and the other two from each pole to ground. at 25 c, switches sw1 through to sw3 have breakdown diode voltages of 320 v. switch sw4 has breakdown diode voltage values of 465 v for the one between poles and 320 v for the two diodes connected to ground. note that only protection to ground is required, as in the limit, the inter-switch voltage limitation of 640 v is the same as the switch to ground limitation of +320 v and -320 v in both polarities. when a switch is in the off state, the maximum withstand voltage may be set by the switch itself or by the control line to the switch. at 25 c, the switch terminal to ground voltage rating for all the switches is 320 v. switches sw1 to sw3 are bidirectional mos types and can withstand 320 v between terminals. switch sw4 is a bidirectional thyristor which is rated at 465 v between terminals. overcurrents as well as overvoltages occur on telephone lines. in the on state, the thyristor switch, sw4, is capable of withst anding high levels of current overload. for currents above about 200 ma, the mos switches, sw1 to sw3, will go into a current limited condition. t his will cause the voltage to rise across the switch and large amounts of power to be developed. in the longer term, this power loss increases the overall chip temperature. when the temperature exceeds about 125 c, thermal shutdown occurs and the switches are set to the off state. without power loss, the lcas will cool. eventually, the thermal trip will reset, setting the switches back in the high power loss condition a gain. the cycle of temperature increase, thermal shutdown, temperature decrease and switch re-activation will continue until the overcurrent cease s. figure 13. lcas shown with switch breakdown limits ring relay slic relay ring generat or sw5a sw5b r1 r2 v bat 2xv ring th1 th2 th3 th4 slic v bat ring tip sw3 sw4 sw1 sw2 control logic + 2xv ring - 2xv ring v bat 0 ring wire tip wire v bat + 2xv ring v bat - 2xv ring v bat 0 ring wire tip wire ground-backed ringing sw5 as shown battery-backed ringing sw5 operated overcurrent protection r1 r2 ai4xar tisp4125m3 or tisp4125h3 tisp4219m3 or tisp4219h3
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection protector voltages protector working and protection voltage design calculations for the lcas are described in the ieee std. c62.37.1-2000, ieee guide for the application of thyristor surge protection devices, pp 40-43. these calculations comprehend: the temprature variation of lcas voltage ratings, increase in protection voltage with ambient temperature rise, long term a.c. heating and under impulse conditions, decrease in working voltage with ambient temperature fall, ground-backed and battery-backed ringing configurations (see figure 13). these calculation techniques were used to set the tisp part voltages. using these tisp parts allows normal system voltage levels of 100 v on tip and 180 v on ring without clipping at 25 c. at 0 c ambient, these voltage levels become 97 v on tip and 174 v on ring. under open circuit line conditions, this means that the peak ringing voltage cannot exceed 174 v for equipment operation down to 0 c ambient. assuming a battery voltage of 48 v 2.5 v and battery-backed ringing, the maximum peak a.c. ring voltage is 174 v - 50.5 v = 123.5 v or 87 v rms. the working voltage of 97 v on tip is more than half the 174 v working voltage on ring. as a result, the tip working voltage does not r epresent a limitation for systems where the tip return resistance is equal or less than the ring source resistance. for balanced impedance ground-backed ringing, the maximum peak a.c. ring voltage under short line conditions (short between tip and ring) is limited by the tip working voltage of 97 v. in the negative ring polarity, the limit of the voltage is made up from half the battery voltage plus half of the peak a.c. ring voltage. the maximum peak a.c. ring voltage is 2 x (97 - 50.5/2) = 143.5 v or 101 v rms . line test voltage levels must be considered, whether they be applied by using lcas switches or separate electro-mechanical rela ys. for these tisp parts, the applied test voltage should not exceed the lowest working voltage, which is 97 v.
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp4xxxh3/m3bj series for lcas protection mechanical data recommended printed wiring footprint device symbolization code devices will be coded as below. as the device parameters are symmetrical, terminal 1 is not identified. smb pad size mdxx bia 2.54 (.10 0) 2.40 (.09 5) 2.16 (.08 5) dimensions are: millimeters (inches) device symbolization code tisp4125h3bj 4125h3 tisp4219h3bj 4219h3 tisp4125m3bj 4125m3 tisp4219m3bj 4219m3
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical data tisp4xxxh3/m3bj series for lcas protection smbj (do-214aa) plastic surface mount diode package this surface mount package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. the compou nd will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated i n high humidity conditions. leads require no additional cleaning or processing when used in soldered assembly. smb mdxxbhaa 2. 00 - 2.40 (.07 9 - .094) 2 1 index mark (if needed) 0. 10 - 0. 20 (.00 4 - .008) 5. 21 - 5.59 (.20 5 - .220) 1. 96 - 2. 32 (.07 7 - .091) 3. 30 - 3. 94 (.13 0 - .155) 4.06 - 4.57 (.16 0 - .180) 0. 76 - 1.52 (.03 0 - .060) 1. 90 - 2.10 (.07 5 - .083) dimensions are: millimeters (inches)
june 2001 ?revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical data tisp4xxxh3/m3bj series for lcas protection t ape dimensions smb package single-sprocket tape notes: a. the clearanc e between the component and the cavity must be within 0.05 mm (.002 in) min. to 0.65 mm (.026 in) max. so that the component cannot rotate more than 20 within the determined cavity. b. tape d devices are supplied on a reel of the following dimensions: reel diameter: 330 mm 3.0 mm (12. 99 in .118 in ) reel hub di ameter: 75 mm (2.95 in) min. reel axia l hole: 13.0 mm 0.5 mm (.512 in .020 in) c. 30 00 devices are on a reel. mdxxbja direct ion of feed 0 min . carrier tape embossment cover ta p e 20 ty pical component cavity center line maximium component r otation ty pical component center line index mark (if needed) 3. 90 - 4.10 (. 154 - .161 ) 1. 95 - 2.05 (.07 7 - .081) 1. 55 - 1.65 (. 061 - .065 ) max . 0. 40 (.01 6) max . 4. 5 (.17 7) max . 8. 20 (.32 3) 11.70 - 12.30 (. 461 - .484 ) 5. 45 - 5.55 (. 215 - .219 ) min . 1. 5 (.05 9) 1. 65 - 1.85 (. 065 - .073 ) 7. 90 - 8 .10 (. 311 - .319 ) ?isp?is a trademark of bourns, ltd., a bourns company, and is registered in u.s. patent and trademark office. ?ourns?is a registered trademark of bourns, inc. in the u.s. and other countries.

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